1. Field
Exemplary embodiments of the present invention relate to a semiconductor device and more particularly, a semiconductor device for controlling a dynamic termination operation.
2. Description of the Related Art
As the capacity and speed of a semiconductor memory device, e.g., Dynamic Random Access Memory (DRAM) is increased and a Double Data Rate Static Dynamic Random Access Memory (DDR SDRAM) is widely used, various new concepts for more increasing a transmission rate of a memory device have been introduced. Among those, a resistance of a termination end is typically employed for smoothly transmitting signals among devices.
In this case, when an impedance-matching is not appropriately provided, the transmitted signals may be reflected and thus, errors may occur during signal transmission. However, when a fixed resistance is applied to the outside, the impedance-matching may not be provided due to aging or temperature change of an integrated circuit or a deviation in a manufacturing process. Therefore, in order to make resistance values equal to each other by comparing with an external reference resistance, a technology for regulating the resistance of the termination end by controlling the number of turned-on transistors among a plurality of transistors connected in parallel has been proposed.
A termination control circuit includes a circuit for controlling activation/inactivation timings of an operation of on die termination, i.e., controlling activation/inactivation timings of a termination circuit (hereinafter, referred to as “a termination”).
According to specifications defined in JEDEC, it is required to support a dynamic on die termination operation (dynamic ODT, hereinafter, referred to as “a dynamic termination”) in a DDR3 SDRAM. The dynamic termination operation includes an operation in which, when a write command is inputted, without resetting of a mode register, the termination resistance in a chip is set to a termination resistance value required at the time of inputting data.
An interface of the semiconductor memory device has different termination types and resistance values at the time to inputting and outputting data. That is, at the time of outputting data, an input/output (DQ) pad is pull-up or pull-down terminated to output logic ‘high’ or logic ‘low’ data. At the time of inputting data, the input/output pad is pull-up and pull-down terminated by a predetermined resistance value which is different from the resistance value at the time of outputting data. Here, the termination regulation at the time of inputting or outputting data is slightly different according to a type of memory devices. The termination circuit in the chip may perform an operation for the data input in response to only the write command in the DDR3 memory device supporting the dynamic termination (dynamic ODT) operation.
That is, a termination control circuit simply serves to control the activation/inactivation of the termination circuit before employing the DDR3, but needs to additionally support the dynamic termination operation in the DDRS memory device.
Therefore, the termination control circuit used in DDR3 memory device activates/inactivates a general termination operation and activates/inactivates the dynamic termination operation.
The difference between the termination operation and the dynamic termination operation will be described hereinafter. The termination operation is controlled at both of inputting and outputting data and is performed in the remaining chips other than chips to and from which data are input/output among a plurality of chips sharing the same input/output pads. The dynamic termination operation is controlled at the time of inputting data and is performed in the chips from which data are inputted among the plurality of chips sharing the same input/output pads.
However, in the DRAM, the termination operation may not be guaranteed when a delay lock loop (DLL) included in the DRAM is inactivated. Therefore, when the write operation is performed if the delay lock loop is inactivated, the impedance matching for the termination end may be not provided, thereby causing an error in writing data.